![]() The input signals J and K are connected to the “Master” flip-flop which locks the input while the clock (Clk) input is high at logic level “1”.Īs the clock input of the “Slave” flip-flop is the inverse (complement) of the “Master” clock input, the outputs from the “Master” flip-flop are only seen by the “Slave” flip-flop when the clock input goes “LOW” to logic level “0”. The clock pulse is given to the master J-K flip flop and it is sent through a NOT Gate and thus inverted before passing it to the slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to the input of the master J-K flip flop. The output of the master J-K flip flop is fed to the input of the slave J-K flip flop. The figure of a master-slave J-K flip flop is shown below.įrom the above figure we can see that both the J-K flip flops are presented in a series connection. Out of these, one acts as the master and receives the external inputs and the other acts as a slave and takes its inputs directly from the master flip-flop. Master-slave J-K flip flop is designed using two J-K flipflops connected in cascade. This problem can be avoided by ensuring that the clock input is at logic “1” only for a very short time.This introduced the concept of Master Slave JK flip flop. This problem is called race around condition in J-K flip-flop. Race Around Condition In JK Flip-flopįor J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain. Each clock pulse toggles the outputs to switch to their opposite states. This off-on action is like a toggle switch and is called toggling. ![]() When J=1 K = 1 and clk = 1, repeated clock pulses cause the output to turn off-on-off-on-off-on and so on. When J =1 K = 0 and clk = 1 output of AND gate connected to J will be Q’ and corresponding NOR gate output will be 0 which the SETs the flipflop. When J =0 K =1 and clk = 1 output of AND gate connected to K will be Q and corresponding NOR gate output will be 0 which RESETs the flipflop. In the hold mode, the data inputs have no effect on the outputs.The outputs “hold” the last data present. When J = K = 0 and clk = 1 output of both AND gates will be 0 when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output or we can say the flip-flop is in the hold (or disabled) mode. ![]() This table shows four useful modes of operation. The truth table of a JK flip flop is shown below. Then the next clock pulse toggles the circuit again from reset to set. Conversely, a “reset” state inhibits input K so that the flip-flop acts as if J=1 and K=0 when in fact both are 1. On the next clock pulse, the outputs will switch or “toggle” from set (Q=1 and Q’=0) to reset (Q=0 and Q’=1). Now what happens when both J and K inputs are 1 !!!!!īecause of the selective inhibiting action of those 3-input AND gates, a “set” state inhibits input J so that the flip-flop acts as if J=0 while K=1 when in fact both are 1. If the circuit is “set,” the J input is inhibited by the 0 status of Q’ through the lower AND gate if the circuit is “reset,” the K input is inhibited by the 0 status of Q through the upper AND gate. In other words, the two inputs are interlocked, so that they cannot both be activated simultaneously. And permit the K input to have effect only when the circuit is set i.e. Now from the above diagram it is clear that, this allows the J input to have effect only when the circuit is reset, i.e. And the third input of each gate receives feedback from the Q and Q’ outputs. The old two-input AND gates of the S-R flip-flop have been replaced with 3-input AND gates. The circuit diagram of the J-K Flip-flop is shown in fig.2. Outputs Q and Q’ are the usual normal and complementary outputs. The input labeled CLK is the clock input. ![]() The inputs labeled J and K are the data inputs ( which used to be S and R inputs in S-R Flip-flop).
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